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타이틀	FPGA NEPP FY10 Summary Report
저자	Sheldon, Douglas
Keyword	CERAMICS;; CHIPS;; DEFECTS;; ELECTRONIC PACKAGING;; FAILURE;; FIELD-PROGRAMMABLE GATE ARRAYS;; REPLACING;; SPACECRAFT DESIGN;; TRANSISTORS
URL	http://hdl.handle.net/2060/20100042162
보고서번호	JPL-Publ-10-8
발행년도	2010
출처	NTRS (NASA Technical Report Server)
ABSTRACT	This report documents the activities and results of the fiscal year 2010 (FY10) funding for the NASA Electronic Parts and Packaging (NEPP) program for Re-programmable Field Programmable Gate Arrays (FPGA). The FY10 task was divided into three efforts. These are listed below: 1. Physics of Failure for the Xilinx Virtex 4 Non-Hermetic Ceramic Flip Chip Column Grid Array Package. 2. Continuation and completion of the IDDQ Study of the Actel A54SX FPGA 3. Actel Flash FPGA Technology The FY10 NEPP FPGA study was organized into these three sections in recognition of the continued and increasing importance of FPGAs to NASA. FPGAs represent the state of the art in electronic components with millions and millions of transistors integrated into a single device. Modern NASA spacecraft design has dozens and dozens of FPGAs implemented onboard. This report found visual defects that are of significant concern for a new proposed flip chip column grid array package. Iddq testing over various combinations of temperature and FPGA resources does not provide enough discrimination to be a replacement for tri-temp testing.